This invention relates to semiconductor electrical translating devices. More particularly, it is concerned with methods of producing mesa diodes having passivated junctions.
The so-called mesa structure has been widely used in certain types of semiconductor diodes. In devices of this type having a P-N junction a mesa or pedestal of semiconductor material extends above the bulk of the body of semiconductor material, and the P-N junction is disposed within the mesa generally parallel to the top surface of the mesa. The edges of the junction at the edge surfaces of the mesa may be protected by a passivating coating as of silicon oxide. For certain applications mesa diodes have advantages over devices of the so-called planar structure in that parasitic capacitance and resistance typically are less and problems inherent in a curved junction are eliminated.
A large number of mesa devices are usually produced simultaneously from a single wafer of semiconductor material typically silicon. For P-N junction devices the junction is formed parallel to the major surfaces of the wafer as by diffusing an appropriate conductivity type imparting material into a surface of the wafer. By employing well-known photoresist masking and etching procedures, the wafer is masked with resistant material and etched to remove the silicon of the diffused region except that which is protected by resistant material, thus forming the mesas. After the mesas are produced, a layer of silicon oxide is formed on the exposed surfaces of the wafer including the surface edges of the mesas. Again employing known photoresist masking and etching procedures, openings are formed in the silicon oxide at the upper surfaces of the mesas. Conductive contacts are applied to the exposed areas of the upper surfaces by employing known metalization techniques. The remaining silicon oxide serves as a passivating layer protecting the edges of the junctions at the edge surfaces of the mesas.
The procedure employed in forming the openings in the silicon oxide layer to expose the upper surfaces of the mesas and thus determine the contact areas causes certain difficulties. The mask employed to define the openings must be carefully aligned with respect to the mesa structure in the wafer. If the entire upper surface of the mesa is not exposed and then metalized, parasitic series resistance through the device is increased. The photoresist material may be too thin at the corners or at the edge surfaces of the mesas with the result that some passivating silicon oxide may be removed from these regions during the etching step. In certain devices a conductive heat sink is mounted on the upper surface of the mesa. If any silicon oxide remains on the upper surface of the mesa, thermal conductivity between the mesa and heat sink is reduced.